`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/08/03 19:45:20
// Design Name: 
// Module Name: BlockRAM
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

//双端口BRAM，一个端口用于读，一个端口用于写，且相互独立
module BlockRAM
#(
    parameter ADDR_WIDTH = 32,
    parameter DATA_WIDTH = 32,
    parameter DEPTH = 1024
)
(
input logic clk,
input logic rst,
//read port
input logic [ADDR_WIDTH-1:0] rd_addr,
output logic [DATA_WIDTH-1:0] rd_data,
//write port
input logic we,
input logic [ADDR_WIDTH-1:0] wr_addr,
input logic [DATA_WIDTH-1:0] wr_data
    );

(*ram_style="block"*)logic [DATA_WIDTH-1:0] bram [0:DEPTH-1];
//read
always_ff@(posedge clk,posedge rst)
if(rst)
    rd_data<=0;
else 
    rd_data<=bram[rd_addr];                    //延迟一个周期读出数据
//write
always_ff@(posedge clk)
if(we)
    bram[wr_addr]<=wr_data;
//end
endmodule
